Semiconductor process technology has been continually scaling down in accordance with the prediction of Moore's law for the past four decades and the trend continues. Shrinking process geometries introduces new physical limitation in the small scale devices. DRAMs (dynamic random access memories) are one of the typical devices receiving great impact on reducing channel length. As the channel length is reduced to increase both the operation speed and the number of components per chip, the so-called short-channel effects arise. One of the physical phenomena attributed to the short-channel effects is the sub-threshold current leakage, and another well-known phenomenon generated by the same effect is the modification of the threshold voltage. The drain-induced barrier lowering (DIBL) contributes to the former phenomenon, wherein a reduction of the potential barrier eventually allows carriers flow between the source and the drain, even if the gate voltage is lower than the threshold voltage; the overestimation of the bulk charge that the gate voltage supports manifests on the threshold voltage shift in the short-channel structure and leads to a drifting threshold voltage that complicate both the control of device operation and the sub-threshold leakage problem. Further more, the small geometry device requires a stringent and precise manufacturing process to retain its reliability, a small window is opened for processing tolerance.
FIG. 1 is a cross-sectional view of a DRAM cell 10 with a conventional gate structure. Two sources 13 and one drain 15 are positioned in a semiconductor substrate 11. A conventional gate 17 is surrounded by a sidewall spacer 19 and is separated from the semiconductor substrate 11 by a thin gate oxide 18. In FIG. 1, two gates, two sources, and one drain form an active region which is further separated by shallow trench isolations (STIs) 12. A double arrow 14 shown in FIG. 1 indicates a channel length in the device structure, as the DRAMs scale down, this channel length becomes shorter and therefore other designs in gate structures are desired to alleviate the short channel effects. Several attempts have been made to mitigate the sub-threshold current leakage and the threshold voltage shift. For example, recessed gate devices were implemented to increase the channel length; devices with heavy channel implantation were also implemented to increase the threshold voltage. Nevertheless, heavy channel implantation effectively raises the threshold voltage, yet it inconvincibly sacrifices the structural integrity of the insulating layer, therefore generate a worse break down voltage.